C952 Computer Architecture is a Western Governors University course on what happens inside the machine that every program runs on.
WGU describes it as an introduction to the organization and architecture of modern computer systems: performance, the processor, memory, input and output (I/O) and multiprocessors, applied to optimizing system design, performance and efficiency. It sits in WGU's computer science curriculum alongside the data structures courses.
Students often find it a shift from programming. The questions are about hardware trade-offs and calculations, and many terms (pipelining, cache associativity, hazards) are new.
Course at a Glance
| Item | Details |
|---|---|
| University | Western Governors University (WGU) |
| Course code | C952 |
| Level | Undergraduate, competency-based |
| Subject area | Computer organization and architecture |
| Core topics | Performance, processor, memory, I/O, multiprocessors |
| Typical work | Concept questions and performance calculations |
What C952 Covers
| Area | What you should be able to do |
|---|---|
| Performance | Calculate CPU time, compare machines and apply Amdahl's law |
| Processor | Explain instruction sets, the datapath, pipelining and hazards |
| Memory | Explain the memory hierarchy, caches and virtual memory |
| I/O | Describe how devices and storage connect to and communicate with the CPU |
| Multiprocessors | Explain parallelism, multicore designs and their limits |
Key Concepts Explained
The CPU Performance Equation
CPU time = instruction count x cycles per instruction (CPI) x clock cycle time. Improving any one factor helps, but changes often trade off against each other.
Example: A program runs 2 billion instructions with an average CPI of 1.5 on a 2 GHz processor (cycle time 0.5 ns). CPU time = 2,000,000,000 x 1.5 x 0.5 ns = 1.5 seconds.
Caches and Average Memory Access Time
Caches keep recently used data close to the processor. Average memory access time (AMAT) = hit time + miss rate x miss penalty.
Example: Hit time 1 cycle, miss rate 5%, miss penalty 100 cycles. AMAT = 1 + 0.05 x 100 = 6 cycles. Halving the miss rate to 2.5% cuts AMAT to 3.5 cycles.
Amdahl's Law and Multiprocessors
The speed-up from improving part of a system is limited by the part that is not improved.
Example: If 80% of a program can run in parallel on 4 cores, speed-up = 1 / (0.2 + 0.8 / 4) = 1 / 0.4 = 2.5 times, not 4.
Pipelining and Hazards
A classic five-stage pipeline splits each instruction into fetch, decode, execute, memory access and write-back. With all stages busy, one instruction can finish every cycle, even though each takes five cycles from start to end.
Hazards break this flow:
- Data hazards: an instruction needs a result that an earlier one has not yet written. Forwarding passes the value directly between stages; otherwise the pipeline stalls.
- Control hazards: after a branch, the processor does not yet know which instruction comes next. Branch prediction guesses, and a wrong guess wastes cycles.
- Structural hazards: two instructions need the same hardware in the same cycle.
Example: An ADD writes register R1 and the very next instruction subtracts using R1. Without forwarding, the second instruction must wait until R1 is written back, adding stall cycles. With forwarding, the result from the execute stage is passed straight to the next instruction's execute stage.
Virtual Memory in One Paragraph
Virtual memory gives each program its own address space, mapped to physical memory in pages. A translation lookaside buffer (TLB) caches recent translations. A page fault occurs when the page is not in memory and must be loaded from storage, which is very slow compared with a cache miss.
Typical Questions and How to Approach Them
| Question type | What it tests | How to approach it |
|---|---|---|
| Performance calculation | Using formulas | Write the formula, convert units, then substitute |
| Pipeline hazards | Understanding the datapath | Identify data, control or structural hazards |
| Cache questions | Memory hierarchy | Split address bits into tag, index and offset |
| Design trade-offs | Judgment | State what improves and what it costs |
Check your WGU course page for the current assessment format and study materials.
Where Students Get Stuck
- Unit conversions. GHz, nanoseconds and cycles get mixed up; convert everything first.
- Pipelining. Draw the stages for several instructions to see where stalls and forwarding happen.
- Cache mapping. Direct-mapped, set-associative and fully associative caches need practice with real addresses.
- Parallel speed-up. Remember the serial part always limits gains.
Study Tips for C952
- Keep a formula sheet with CPU time, AMAT and Amdahl's law, plus one solved example of each.
- Draw the memory hierarchy from registers to disk with rough speeds and sizes.
- Explain each concept in your own words before attempting practice questions.
- Revisit weak areas with short daily practice instead of one long session.
How We Help with C952
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Frequently Asked Questions
The organization and architecture of modern computers: performance, the processor, memory, I/O and multiprocessors.
It uses a few key formulas, such as CPU time, AMAT and Amdahl's law. The arithmetic is simple once units are handled carefully.
Overlapping the stages of several instructions, like an assembly line, so the processor completes more instructions per unit of time.
Main memory is far slower than the processor, so a good cache hit rate has a large effect on overall performance.
Amdahl's law: the part of a program that must run serially limits the overall gain.
Yes, with notes and practice calculations. We do not sit exams or access your WGU account.