For the following VHDL code, Is it necessary to keep

For the following VHDL code, Is it necessary to keep the variables KM2, KM1, KN2, KN1 ? This is a delay code and all these variables are equal to the input signal “Key” and the output is always zero.

Can I do,

KM1 <=>

KM <= km1=”” or=”” km1;=””>

Code ——

——————-÷——————–
library ieee;
use ieee.std_logic_1164.all;
————————————-
entity Press_Button is — to initialize the zoom in/out keys.
generic(SIZE : integer := 5);
port(
clk : in std_logic;
KEY : in std_logic_vector(SIZE-1 downto 0); — Delay the key: We neeed delay because
OutKey : out std_logic_vector(SIZE-1 downto 0)
);
end Press_Button;
———————————–
architecture Behavioral of Press_Button is

signal KM : std_logic_vector(SIZE-1 downto 0):=(others=>’1′);
signal KM1 : std_logic_vector(SIZE-1 downto 0):=(others=>’1′);
signal KM2 : std_logic_vector(SIZE-1 downto 0):=(others=>’1′);

signal KN1 : std_logic_vector(SIZE-1 downto 0):=(others=>’1′);
signal KN2 : std_logic_vector(SIZE-1 downto 0):=(others=>’1′);

signal cnt_20ms : integer :=0;
signal clk_20ms : std_logic:=’0′;

begin

process(clk)
begin
if(clk’event and clk = ‘1’) then — they want nothing to happen. This process works before the second one that is how it delays.
if(cnt_20ms
cnt_20ms<>
clk_20ms<=not clk_20ms;=”” –=”” controls=”” the=”” second=”” process.=”” delays=””>
else
cnt_20ms<>
end if;
end if;
end process;

process(clk_20ms)
begin
if(clk_20ms’event and clk_20ms = ‘1’) then — inputs cannot be on the left side of the process. Outputs cannot be on the right.
KM1<=key; –=”” creating=”” temp=””>
KM2<>
KM<=km1 or=””>
end if;
end process;

process(clk) — general 100 MHZ
begin
if(clk’event and clk = ‘1’) then
KN1<=km; –=”” km=”” is=”” same=”” as=”” the=””>
KN2<>
OutKey<=(kn1 and=”” (not=”” kn2));=”” –the=”” output=”” is=”” always=”” zero.=”” because=”” we=”” dont=”” want=”” it=”” to=”” do=”” anything.=”” just=”” delays=”” the=””>
end if;
end process;

end Behavioral;